This invention relates to electronic signal transmission, and more particularly to using all-digital Phase-locked loops (PLL's) in modulators and demodulators.
Digital implementations of phase-locked loops (PLL's) are widely used in various applications, such as digital communications and clock/data recovery. Conventional implementations of digital phase-locked loops normally use a numerically controlled oscillator (NCO) as the frequency source. An NCO (also known as a digitally controlled oscillator or DCO), particularly one implemented as counter, suffers from phase resolution or frequency granularity at high frequency.
Another type of digital PLL uses a set of multi-phase clocks rather than a variable-frequency oscillator. Using Multi-phase clocks can improve the phase resolution of digitally implemented oscillators. Phase resolution is improved by sequentially selecting a phase (in ascending and descending order) from the multiphase clocks and then feeding the selected phase to a clock divider. Thus, a variable digital oscillator is constructed whose phase can be finely adjusted without altering the nominal oscillation frequency.
Analog components, such as a tapped delay line or a voltage-controlled oscillator (VCO), have been used for some oscillator applications, such as modulating or de-modulating signals in communications systems. However, these analog components are difficult to integrate with large digital system chips. Thus all-digital oscillators are preferable.
FIG. 1 shows a prior-art digital PLL using multi-phase clocks instead of a variable-frequency oscillator. The loop includes phase detector 10, up/down counter 12, phase rotator 14, and divider 18. Multi-phase clocks 20 have different phase offsets that are spaced equally and in a sequence. Multi-phase clocks 20 are applied to phase rotator 14, which selects one of the multi-phase clocks 20 as the output clock OUT_CLK.
Phase detector 10 compares the phase of input clock IN_CLK to the phase of feedback clock FB_CLK from divider 18. When the phase of the feedback clock lags the phase of the input clock, phase detector 10 generates a signal to decrement up/down counter 12. Decrementing up/down counter 12 causes phase rotator 14 to select a multiphase clock from multi-phase clocks 20 with a leading phase. Conversely, when the phase of the feedback clock leads the phase of the input clock, phase detector 10 generates a signal to increment up/down counter 12. Incrementing up/down counter 12 causes phase rotator 14 to select from multi-phase clocks 20 a multiphase clock with a lagging phase. Thus, a digital feedback loop is created that allows the phase of the feedback clock (and output clock) to track the phase of the input clock.
Up/down counter 12 can be a modulo-M counter that is updated every cycle of the feedback clock. Hence, the phase of the feedback clock in each clock cycle can only change by one phase increment of the multiphase clocks. The selected phase φ R from multiphase clocks φ [0:M−1] is selected by phase rotator 14 and applied to divider 18.
Multi-phase clock generator 16 generates multi-phase clocks 20 from a reference clock REF_CLK. A ring oscillator or a delay-locked loop (DLL) can be used for multi-phase clock generator 16. Differential buffers or standard inverters can be used in a ring or delay line, and the oscillation frequency can be changed by adjusting a bias to the buffers or inverters, such as a bias for a current source or sink.
The frequency of multi-phase clocks 20 can be an Nth multiple of the input signal frequency of IN_CLK. This permits phase selection by phase rotator 14, and the phase adjustment on the output clock, to have M×N resolutions.
However, IN_CLK and REF_CLK may be asynchronous. When the frequency of multi-phase clocks 20 is not an Nth multiple of the input clock IN_CLK, a frequency offset exists. Phase rotator 14 will constantly rotate forward or backward in phase in order to accommodate the frequency difference between the input clock and multi-phase clocks 20.
FIG. 2 is a waveform diagram showing multi-phase clocks. In this example M is 8, so that 8 multi-phase clocks φ 0-φ 7 are generated by the multi-phase clock generator. Each pair of adjacent multi-phase clocks are offset from each other in phase by one-eighth of the clock period of the multi-phase clocks. The phase rotator selects one of these multi-phase clocks as the output clock in response to the current count of the up/down counter.
While such digital PLL's that employ multi-phase clocks are useful as basic oscillators for generating clocks, the use of these digital PLL's in other applications is desirable. In particular, the use of multi-phase clocks for signaling and communication systems is desirable. Rather than simply use a digital PLL to generate fixed-frequency clocks, it is desired to modulate the frequency to encode signals, such as with phase modulation and frequency modulation (FM). It is desired to encode and decode signals for transmission using multi-phase clocks and a structure similar to a digital PLL. An all-digital phase modulator and demodulator using multi-phase clock rotation is desirable.